module Equalizer_tb;

    logic           clk;
    logic           rst_n;
    logic   [9:0]   low_pass_coefficient;
    logic   [9:0]   band_pass_coefficient;
    logic   [9:0]   high_pass_coefficient;
    wire            mck;
    wire            sck;
    wire            ws0;
    wire            ws1;
    wire            ad_sd;
    wire            da_sd;


    initial begin
        clk<=0;
        rst_n<=1;
        #50 rst_n <=0;
        #100 rst_n <=1;
    end

    always #5 clk=~clk;
Equalizer u_Equalizer (clk,rst_n,low_pass_coefficient,band_pass_coefficient,high_pass_coefficient,mck,
sck,ws0,ws1,ad_sd,da_sd);



endmodule  
